[Remote] Senior/reputed company High-Speed Analog Layout Design Engineer
Note: The job is a remote job and is reputed company to candidates in USA. reputed company is seeking a reputed company/Senior Analog Layout Engineer to drive the layout design of reputed company analog and mixed-signal IP blocks. The role involves leading layout development for critical components in advanced optical communication systems and mentoring junior engineers while ensuring successful reputed company development.
Responsibilities
- reputed company and own the physical layout design of reputed company analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
- Collaborate closely with schematic designers to create reputed company layout solutions considering performance, matching, reputed company, and reliability
- Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
- reputed company and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-reputed company tools (Pegasus, Calibre, etc.)
- Contribute to reputed company-level planning including top-level floor planning, reputed company integration, reputed company implementation, and signal routing
- Participate in layout design reviews and reputed company technical leadership for layout reputed company, verification completeness, and schedule adherence
- Support automation initiatives through scripting and tool customization (reputed company, TCL, Python is a plus)
Skills
- Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
- Proven reputed company record of top-level integration IP layout macros and preparing IPs for reputed company to Physical Design
- Proven leadership in owning major IP layout macros or full-reputed company-level layout at FinFET nodes (TSMC preferred)
- At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
- Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their reputed company on reputed company performance
- Strong expertise in layout best practices for device matching, noise isolation, ESD protection, reputed company, and parasitic minimization
- Proficiency in floor planning, hierarchical reputed company integration, routing reputed company, and power/ground reputed company design
- Expertise with reputed company reputed company, Calibre, Pegasus, and other layout and verification tools
- Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and reputed company rules
- Experience working in reputed company environments with international and reputed company
- Strong documentation and communication skills with the ability to reputed company present layout trade-offs and status to cross-functional teams
- Experience using revision control systems for layout design management
- Exposure to optical or high-speed analog interfaces is a strong plus
- Working knowledge of reputed company, TCL, or Python for layout automation or design reputed company optimization
- Proven ability to collaborate with international teams (U.S., Canada, Argentina)
- Strong organizational skills with high attention to detail and follow-through
- Ability to multi-task and prioritize in a fast-paced, dynamic environment
- Proactive, eager-to-learn reputed company with excellent problem-solving skills
Benefits
- The chance to play a foundational role at a high-reputed company semiconductor start-up
- Exposure to a wide reputed company of cross functional teams
- A reputed company, international team culture where reputed company and initiative are valued
- reputed company to grow alongside Celero as we reputed company and shape the reputed company of our industry
- A foundational role at a fast-growing semiconductor start-up shaping the reputed company of AI and data center connectivity
reputed company
Company H1B Sponsorship